Semiconductor structure

ABSTRACT

A semiconductor structure includes a silicon substrate, an aluminum nitride layer and a plurality of grading stress buffer layers. The aluminum nitride layer is disposed on the silicon substrate. The grading stress buffer layers are disposed on the aluminum nitride layer. Each grading stress buffer layer includes a grading layer and a transition layer stacked up sequentially. A chemical formula of the grading layer is Al 1−x Ga x N, wherein the x value is increased from one side near the silicon substrate to a side away from the silicon substrate, and 0≦x≦1. A chemical formula of the transition layer is the same as the chemical formula of a side surface of the grading layer away from the silicon substrate. The chemical formula of the transition layer of the grading stress buffer layer furthest from the silicon substrate is GaN.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 101145835, filed on Dec. 6, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor structure. More particularly, the invention relates to a semiconductor structure having grading stress buffer layers.

2. Description of Related Art

With the progress of semiconductor technologies, a light emitting diode (LED) now has advantages of high luminance, low power consumption, compactness, low driving voltage, being mercury free, and so forth. Therefore, the LED has been extensively applied in the field of displays and illumination. In general, an LED chip is fabricated by using a broad band-gap semiconductor material, such as gallium nitride (GaN). However, in addition to the difference in thermal expansion coefficient and chemical properties, the difference between the lattice constant of GaN and that of a hetero-substrate cannot be ignored. Hence, due to lattice mismatch, GaN grown on the hetero-substrate undergoes lattice dislocation, and the lattice dislocation extends toward a thickness direction of the GaN layer. Further, because of lattice mismatch between GaN and the hetero-substrate, the material of GaN relative to the hetero-substrate will create great structural stress. As the growth thickness becomes thicker, the stress accumulated becomes greater. When exceeding a threshold value, the material layer will be unable to support the stress, and must deform to release the stress. As such, the lattice dislocation not only causes crystal growth defects which reduce the light emitting efficiency of the LED and shortens lifetime, it also can not grow very thick GaN.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor structure, capable of releasing the stress problem caused by conventional lattice mismatch, and reducing lattice dislocation from extending in a thickness direction.

The invention provides a semiconductor structure, including a silicon substrate, an aluminum nitride layer, and a plurality of grading stress buffer layers. The aluminum nitride layer is disposed on the silicon substrate. The grading stress buffer layers are disposed on the aluminum nitride layer. Each grading stress buffer layer includes a grading layer and a transition layer stacked up sequentially. A chemical formula of the grading layer is Al_(1−x)Ga_(x)N, wherein the x value is increased from one side near the silicon substrate to a side away from the silicon substrate, and 0≦x≦1. A chemical formula of the transition layer is the same as the chemical formula of a side surface of the grading layer away from the silicon substrate. The chemical formula of the transition layer of the grading stress buffer layer furthest away from the silicon substrate is GaN.

In an embodiment of the invention, the thickness of the grading layer of the grading stress buffer layers increase from a side close to the silicon substrate to a side away from the silicon substrate.

In an embodiment of the invention, the thickness of each grading layer ranges from 50 nm to 700 nm.

In an embodiment of the invention, the thickness of the transition layer of the grading stress buffer layers increase from a side close to the silicon substrate to a side away from the silicon substrate.

In an embodiment of the invention, the thickness of each transition layer ranges from 50 nm to 700 nm.

In an embodiment of the invention, the x value of the chemical formula of the transition layer increases as an arithmetic progression.

In an embodiment of the invention, the grading stress buffer layers include 2 to 10 grading stress buffer layers.

In an embodiment of the invention, the semiconductor structure further includes a superlattice structure layer, disposed between the aluminum nitride layer and the plurality of grading stress buffer layers. The superlattice structure layer includes a plurality of aluminum gallium indium nitride structure layers. Each aluminum gallium indium nitride structure layer includes a first aluminum gallium indium nitride layer and a second aluminum gallium indium nitride layer stacked on each other. The chemical formula of the first aluminum gallium indium nitride layers is Al_(s)Ga_(t)In_((1-s-t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1. The chemical formula of the second aluminum gallium indium nitride layers is Al_(m)Ga_(n)In_((1-m-n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1. When m=s, n≠t, and when n=t, m≠s.

In an embodiment of the invention, the thickness of each aluminum gallium indium nitride structure layer ranges from 5 nm to 500 nm.

In an embodiment of the invention, the thickness of the superlattice structure layer ranges from 20 nm to 5000 nm.

In an embodiment of the invention, the superlattice structure layer includes 5 or more aluminum gallium indium nitride structure layers.

In an embodiment of the invention, the semiconductor structure further includes a superlattice structure layer, disposed between the plurality of grading stress buffer layers. The superlattice structure layer includes a plurality of aluminum gallium indium nitride structure layers. Each aluminum gallium indium nitride structure layer includes a first aluminum gallium indium nitride layer and a second aluminum gallium indium nitride layer stacked on each other. The chemical formula of the first aluminum gallium indium nitride layers is Al_(s)Ga_(t)In_((1-s-t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1. The chemical formula of the second aluminum gallium indium nitride layers is Al_(m)Ga_(n)In_((1-m-n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1. When m=s, n≠t, and when n=t, m≠.

In an embodiment of the invention, the thickness of each aluminum gallium indium nitride structure layer ranges from 5 nm to 500 nm.

In an embodiment of the invention, the thickness of the superlattice structure layer ranges from 20 nm to 5000 nm.

In an embodiment of the invention, the superlattice structure layer includes 5 or more aluminum gallium indium nitride structure layers.

Based on the above, since a plurality of grading stress buffer layers are disposed on the aluminum nitride layer of the invention, the amount of gallium can be increased, so as to achieve a GaN layer. As such, the stress generated from the lattice difference between the GaN layer and the silicon substrate can be effectively reduced. In addition, lattice dislocation extending in a thickness direction can also be effectively reduced, improving the overall quality of the semiconductor structure.

Several exemplary embodiments accompanied with figures are described in detail below to further describe the invention in details.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the invention.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the invention.

DESCRIPTION OF EMBODIMENTS

In the description of the following embodiments, when a layer (or film) or a structure is disposed “above” or “below” another substrate, another layer (or film), or another structure, it should be understood that the layer (or film) or the structure can be “directly” located on another substrate, layer (or film), or another structure. Or, the two layers (or films) or structures can have one or more middle layers so as to be “indirectly” disposed on each other. The Examiner can refer to the attached figures for the position of each layer.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. Referring to FIG. 1, in the embodiment, a semiconductor structure 100 a includes a silicon substrate 110, an aluminum nitride layer 120, and a plurality of grading stress buffer layers 140 a, 140 b, 140 c, and 140 d (FIG. 1 only shows four). The silicon substrate 110 has an upper surface 112. The aluminum nitride layer 120 is disposed on the upper surface 112 of the silicon substrate 110. The grading stress buffer layers 140 a, 140 b, 140 c, and 140 d are disposed on the aluminum nitride layer 120. Each grading stress buffer layer 140 a (or 140 b, 140 c, 140 d) includes a grading layer 142 a (or 142 b, 142 c, 142 d) and a transition layer 144 a (or 144 b, 144 c, 144 d) stacked up sequentially. A chemical formula of the grading layers 142 a, 142 b, 142 c, 142 d is Al_(1−x)Ga_(x)N, wherein the x value is increased from one side near the upper surface 112 of the silicon substrate 110 to a side away from the upper surface 112 of the silicon substrate 110, and 0≦x≦1. Each transition layer 144 a (or 144 b, 144 c, 144 d) and a side surface 1422 a (or 1422 b, 1422 c, 1422 d) of each grading layer 142 a (or 142 b, 142 c, 142 d) furthest away from the silicon substrate is made up of the same elements.

For example, the x value of the chemical formula of the grading layer 142 a of the grading stress buffer layer 140 a is, for example, between 0 and 0.25. That is to say, the Al amount of the grading layer 142 a decreases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Al amount decreases from 1 to 0.75). The Ga amount increases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Ga amount increases from 0 to 0.25). The transition layer 144 a and the side surface 1422 a of the grading layer 142 a furthest from the silicon substrate 110 are made up of the same elements (i.e. the chemical formula of the transition layer 144 a is Al_(0.75)Ga_(0.25)N).

Similarly, the x value of the chemical formula of the grading layer 142 b of the grading stress buffer layer 140 b is, for example, between 0.25 and 0.5. That is to say, the Al amount of the grading layer 142 b decreases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Al amount decreases from 0.75 to 0.5). The Ga amount increases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Ga amount increases from 0.25 to 0.5). The transition layer 144 b and the side surface 1422 b of the grading layer 142 b furthest from the silicon substrate are made up of the same elements (i.e. the chemical formula of the transition layer 144 b is Al_(0.5)Ga_(0.5)N).

The x value of the chemical formula of the grading layer 142 c of the grading stress buffer layer 140 c is, for example, between 0.5 and 0.75. That is to say, the Al amount of the grading layer 142 c decreases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Al amount decreases from 0.5 to 0.25). The Ga amount increases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Ga amount increases from 0.5 to 0.75). The transition layer 144 c and the side surface 1422 c of the grading layer 142 c furthest from the silicon substrate are made up of the same elements (i.e. the chemical formula of the transition layer 144 c is Al_(0.25)Ga_(0.75)N).

The x value of the chemical formula of the grading layer 142 d of the grading stress buffer layer 140 d is, for example, between 0.75 and 1. That is to say, the Al amount of the grading layer 142 d decreases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Al amount decreases from 0.25 to 0). The Ga amount increases from a side close to the aluminum nitride layer 120 to a side away from the aluminum nitride layer 120 (i.e. the Ga amount increases from 0.75 to 1). Specifically, the transition layer 144 d of the grading stress buffer layer 140 d furthest from the silicon substrate 110 and the side surface 1422 d of the grading layer 142 d furthest from the silicon substrate are made up of the same elements (i.e. the chemical formula of the last transition layer 144 d is GaN).

That is to say, the x value (i.e. the gallium amount) of the chemical formula of the transition layers 144 a, 144 b, 144 c, 144 d of the grading stress buffer layers 140 a, 140 b, 140 c, 140 d increases as an arithmetic progression, and the aluminum amount decreases with a proportional arithmetic progression. Of course, in other embodiments, the x value of the chemical formula of the transition layers 144 a, 144 b, 144 c, 144 d can increase without an arithmetic progression, and is not limited thereto.

Furthermore, the thicknesses h1, h2, h3, h4 of the grading layers 142 a, 142 b, 142 c, 142 d of the grading stress buffer layers 140 a, 140 b, 140 c, 140 d increase from close to an upper surface 112 of the silicon substrate 110 to away from the upper surface 112 of the silicon substrate 110. That is to say, the thickness h1 of the grading layer 142 a is less than the thickness h2 of the grading layer 142 b. The thickness h2 of the grading layer 142 b is less than the thickness h3 of the grading layer 142 c. The thickness h3 of the grading layer 142 c is less than the thickness h4 of the grading layer 142 d. Herein, preferably, the thickness h1 (or h2, h3, h4) of each grading layer 142 a (or 142 b, 142 c, 142 d) ranges between 50 nm and 700 nm. It should be noted that with the thicknesses of the grading layers falling within this range, the growth quality is more stable and will be less likely to have defects.

In addition, the thicknesses of the transition layers 144 a, 144 b, 144 c, 144 d of the grading stress buffer layers 140 a, 140 b, 140 c, 140 d increase from close to an upper surface 112 of the silicon substrate 110 to away from the upper surface 112 of the silicon substrate 110. That is to say, the thickness h1′ of the transition layer 144 a is less than the thickness h2′ of the transition layer 144 b. The thickness h2′ of the transition layer 144 b is less than the thickness h3′ of the transition layer 144 c. The thickness h3′ of the transition layer 144 c is less than the thickness h4′ of the transition layer 144 d. Herein, preferably, the thickness h1′ (or h2′, h3′, h4′) of each transition layer 144 a (or 144 b, 144 c, 144 d) ranges between 50 nm and 700 nm. It should be noted that with the thicknesses of the transition layers falling within this range, the growth quality is more stable and will be less likely to have defects.

In the semiconductor structure 100 a of the embodiment, the grading stress buffer layers 140 a, 140 b, 140 c, 140 d are disposed on the aluminum nitride layer 120. The aluminum amount in the transition layers 144 a, 144 b, 144 c, 144 d decreases as an arithmetic progression, and the gallium amount increases as an arithmetic progression. The transition layer 144 a, 144 b, 144 c, 144 d and the side surface 1422 a (or 1422 b, 1422 c, 1422 d) of the grading layer 142 a, 142 b, 142 c, 142 d furthest from the silicon substrate 110 are made up of the same aluminum amount and gallium amount. Thus, a GaN layer can be obtained (i.e. transition layer 144 d). The grading stress buffer layers 140 a, 140 b, 140 c, 140 d can be used to reduce the stress caused by the expansion coefficient and the lattice difference between the GaN layer (i.e. the transition layer 144 d) and the silicon substrate 110. Besides the grading stress buffer layers 140 a, 140 b, 140 c, 140 d having the function of relieving stress, conventional lattice dislocation extending in a thickness direction can also be reduced, improving the overall quality of the semiconductor structure 100 a.

Of course, the number of the grading stress buffer layers 140 a, 140 b, 140 c, 140 d shown are exemplary. One skilled in the art can adjust the amount of aluminum and gallium and increase the number of grading stress buffer layers. If the x value (i.e. the gallium amount) increases by an arithmetic progression of 0.1, the number of grading stress buffer layers can be 10. This way, the stress caused by the expansion coefficient and the lattice difference between the GaN layer (i.e. the transition layer 144 d) and the silicon substrate 110 can be reduced; details are not repeated herein.

It is noted that the following embodiment uses the same reference numerals and partial content of the previous embodiment. The same reference numerals represent similar components, and repeated description is omitted. Those not described in the following embodiment can be referred to in the above embodiment.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the invention. Referring to FIG. 2, the semiconductor structure 100 b of the embodiment is similar to the semiconductor structure 100 a of FIG. 1. The difference between the two is that the semiconductor structure 100 b of the embodiment further includes a superlattice structure layer 150 a. The superlattice structure layer 150 a is disposed between the aluminum nitride layer 120 and the grading stress buffer layers 140 a, 140 b, 140 c, 140 d.

In detail, the superlattice structure layer 150 a is disposed between the aluminum nitride layer 120 and the grading stress buffer layer 140 a. The super lattice structure layer 150 a includes a plurality of aluminum gallium indium nitride structure layers 152 a 1, 152 a 2 (FIG. 2 only shows two). Each aluminum gallium indium nitride structure layer 152 a 1 (or 152 a 2) includes a first aluminum gallium indium nitride layer 151 a 1 (or 151 a 2) and a second aluminum gallium indium nitride layer 153 a 1 (or 153 a 2) stacked on each other. The chemical formula of the first aluminum gallium indium nitride layers 151 a 1, 151 a 2 is Al_(s)Ga_(t)In_((1-s-t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1. The chemical formula of the second aluminum gallium indium nitride layers 153 a 1, 153 a 2 is Al_(m)Ga_(n)In_((1-m-n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1. When m=s, n≠t, and when n=t, m≠s. That is to say, the ratio of the elements of the first aluminum gallium indium nitride layer 151 a 1 (or 151 a 2) and the second aluminum gallium indium nitride layer 153 a 1 (or 153 a 2) are not exactly the same.

For example, the chemical formula of the first aluminum gallium indium nitride layer 151 a 1 of the aluminum gallium indium nitride structure layer 152 a 1 is Al_(0.3)Ga_(0.2)In_(0.5)N, and the chemical formula of the second aluminum gallium indium nitride layer 153 a 1 is Al_(0.3)Ga_(0.4)In_(0.3)N. In addition, the thickness t1, t2 of each aluminum gallium indium nitride structure layer 152 a 1, 152 a 2 ranges, for example, from 5 nm to 500 nm. The thickness t of the superlattice structure 150 a, for example, ranges from 20 nm to 5000 nm. Preferably, the number of aluminum gallium indium nitride structure layers 152 a 1, 152 a 2 is at least five. Because the superlattice structure 150 a is disposed between the aluminum nitride layer 120 and the grading stress buffer layer 140 a, the design can help in reducing the stress caused by the expansion coefficient and the lattice difference between the grading stress buffer layer 140 a and the silicon substrate 110. In addition, the dislocation formed before the superlattice structure 150 a is grown can be prevented, so that the dislocation is unable to continue to grow. This further improves the quality of the semiconductor structure 100 b.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the invention. Referring to FIG. 3, the semiconductor structure 100 c of the embodiment is similar to the semiconductor structure 100 a of FIG. 1. The difference between the two is that the semiconductor structure 100 c of the embodiment further includes a superlattice structure layer 150 b. The superlattice structure layer 150 b is disposed between the grading stress buffer layer 140 a and the grading stress buffer layer 140 b. The superlattice structure layer 150 b includes a plurality of aluminum gallium indium nitride structure layers 152 b 1, 152 b 2. Each aluminum gallium indium nitride structure layer 152 b 1 (or 152 b 2) includes a first aluminum gallium indium nitride layer 151 b 1 (or 151 b 2) and a second aluminum gallium indium nitride layer 153 b 1 (or 153 b 2) stacked on each other. The chemical formula of the first aluminum gallium indium nitride layers 151 b 1, 151 b 2 is Al_(s)Ga_(t)In_((1-s-t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1. The chemical formula of the second aluminum gallium indium nitride layers 153 b 1, 153 b 2 is Al_(m)Ga_(n)In_((1-m-n)))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1. When m=s, n≠t, and when n=t, m≠s. That is to say, the ratio of the elements of the first aluminum gallium indium nitride layer 151 b 1 (or 151 b 2) and the second aluminum gallium indium nitride layer 153 b 1 (or 153 b 2) are not exactly the same.

For example, the chemical formula of the first aluminum gallium indium nitride layer 151 b 1 of the aluminum gallium indium nitride structure layer 152 b 1 is Al_(0.3)Ga_(0.2)In_(0.5)N, and the chemical formula of the second aluminum gallium indium nitride layer 153 b 1 is Al_(0.3)Ga_(0.4)In_(0.3)N. In addition, the thickness t1′, t2′ of each aluminum gallium indium nitride structure layer 152 b 1, 152 b 2 ranges, for example, from 5 nm to 500 nm. The thickness t′ of the superlattice structure 150 b, for example, ranges from 20 nm to 5000 nm. Preferably, the number of aluminum gallium indium nitride structure layers 152 b 1, 152 b 2 is at least five. Because the superlattice structure 150 a is disposed between the adjacent grading stress buffer layers 140 a, 140 b, the design can help in reducing the stress caused by the expansion coefficient and the lattice difference between the grading stress buffer layers 140 a, 140 b. In addition, the dislocation formed before the superlattice structure 150 b is grown can be prevented, so that the dislocation is unable to continue to grow. This further improves the quality of the semiconductor structure 100 c.

It should be noted that the invention does not limit the position and type of the superlattice structures 150 a, 150 b even though the superlattice structures 150 a, 150 b have been to described to be located between the aluminum nitride layer 120 and the grading stress buffer layer 140 a, or, between the grading stress buffer layer 140 a and the grading stress buffer layer 140 b. In other embodiments not shown, the superlattice structure can be disposed between any two neighboring layers of the grading stress buffer layers 140 a, 140 b, 140 c, 140 d; for example, between the grading layer 142 a and the transition layer 144 a, or the grading layer 142 c and the transition layer 144 c. Or, the superlattice structures can at the same time be disposed between the aluminum nitride layer 120 and the grading stress buffer layer 140 a, and between any two neighboring layers of the grading stress buffer layers 140 a, 140 b, 140 c, 140 d. One skilled in the art can adjust or increase the design of the superlattice structures accordingly, so as to satisfy reducing of dislocation. This is still a part of the technical proposal of the invention and does not depart from the protection scope of the invention.

To sum up, since a plurality of grading stress buffer layers are disposed on the aluminum nitride layer of the invention, the amount of gallium can be increased, so as to achieve a GaN layer. Therefore, the stress generated from the lattice difference between the GaN layer and the silicon substrate can be effectively reduced. In addition, lattice dislocation extending in a thickness direction can also be effectively reduced, improving the overall quality of the semiconductor structure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this specification provided they fall within the scope of the following claims and their equivalents. 

What is claimed is:
 1. A semiconductor structure, comprising: a silicon substrate; an aluminum nitride layer disposed on the silicon substrate; and a plurality of grading stress buffer layers disposed on the aluminum nitride layer, wherein each of the grading stress buffer layers includes a grading layer and a transition layer stacked up sequentially, a chemical formula of each of the grading layers is Al_(1−x)Ga_(x)N, wherein an x value is increased from a side near the silicon substrate to a side away from the silicon substrate, and 0≦x≦1, wherein a chemical formula of each of the transition layers is the same as a chemical formula of a side surface furthest away from the silicon substrate of each of the corresponding grading layers, and a chemical formula of the transition layer of the grading stress buffer layer furthest away from the silicon substrate is GaN.
 2. The semiconductor structure as claimed in claim 1, wherein a thickness of each of the grading layers of the grading stress buffer layers increase from a side close to the silicon substrate to a side away from the silicon substrate.
 3. The semiconductor structure as claimed in claim 2, wherein the thickness of each of the grading layers is between 50 nm and 700 nm.
 4. The semiconductor structure as claimed in claim 1, wherein a thickness of each of the transition layers of the grading stress buffer layers increase from a side close to the silicon substrate to a side away from the silicon substrate.
 5. The semiconductor structure as claimed in claim 4, wherein the thickness of each of the transition layers is between 50 nm and 700 nm.
 6. The semiconductor structure as claimed in claim 1, wherein the x value of the chemical formula of the transition layers increases as an arithmetic progression.
 7. The semiconductor structure as claimed in claim 1, wherein a number of the grading stress buffer layers is 2 to 10 grading stress buffer layers.
 8. The semiconductor structure as claimed in claim 1, further comprising a superlattice structure layer, disposed between the aluminum nitride layer and the plurality of grading stress buffer layers, wherein the superlattice structure layer includes a plurality of aluminum gallium indium nitride structure layers, each of the aluminum gallium indium nitride structure layers includes a first aluminum gallium indium nitride layer and a second aluminum gallium indium nitride layer stacked on each other, a chemical formula of the first aluminum gallium indium nitride layers is Al_(s)Ga_(t)In_((1-s-t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1, and a chemical formula of the second aluminum gallium indium nitride layers is Al_(m)Ga_(n)In_((1-m-n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1, and when m=s, n≠t, and when n=t, m≠s.
 9. The semiconductor structure as claimed in claim 8, wherein a thickness of each of the aluminum gallium indium nitride structure layers is between 5 nm and 500 nm.
 10. The semiconductor structure as claimed in claim 9, wherein the thickness of the superlattice structure layer is between 20 nm and 5000 nm.
 11. The semiconductor structure as claimed in claim 8, wherein the superlattice structure layer includes 5 or more aluminum gallium indium nitride structure layers.
 12. The semiconductor structure as claimed in claim 1, further comprising a superlattice structure layer, disposed between the plurality of grading stress buffer layers, wherein the superlattice structure layer includes a plurality of aluminum gallium indium nitride structure layers, each of the aluminum gallium indium nitride structure layers includes a first aluminum gallium indium nitride layer and a second aluminum gallium indium nitride layer stacked on each other, a chemical formula of the first aluminum gallium indium nitride layers is Al_(s)Ga_(t)In_((1-s-t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1, and a chemical formula of the second aluminum gallium indium nitride layers is Al_(m)Ga_(n)In_((1-m-n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1, and when m=s, n≠t, and when n=t, m≠s.
 13. The semiconductor structure as claimed in claim 12, wherein a thickness of each of the aluminum gallium indium nitride structure layers is between 5 nm and 500 nm.
 14. The semiconductor structure as claimed in claim 13, wherein the thickness of the superlattice structure layer is between 20 nm and 5000 nm.
 15. The semiconductor structure as claimed in claim 12, wherein the superlattice structure layer includes 5 or more aluminum gallium indium nitride structure layers. 